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Martin Whitaker
c1f750ff98
If a function in a continuous assignment is passed an array word as
an argument, syntactically incorrect vvp code is generated. This is
because the code calls draw_net_input to generate the input labels
part way through writing out the .ufunc statement. If an input is
an array word, draw_net_input causes a .array/port statement to be
emitted, which gets written out in the middle of the .ufunc statement.
This patch fixes the problem by collecting the necessary input labels
prior to starting writing the .ufunc statement.
(cherry picked from commit 9950704735)
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.