46 lines
721 B
Verilog
46 lines
721 B
Verilog
`timescale 1s/1ms
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module test;
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logic [3:0] v4;
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wire [3:0] w4;
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integer i4;
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bit [3:0] v2;
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byte b2;
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shortint s2;
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int i2;
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longint l2;
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real r;
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event e;
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logic [3:0] p4;
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logic [3:0] a4[3:0];
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bit [3:0] a2[3:0];
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assign w4 = v4;
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initial begin
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$my_monitor(v4, w4, i4, v2, b2, s2, i2, l2, r, e, p4[1:0], a4, a2[1]);
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#1 v4 = 4'd1;
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#1 i4 = 2;
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#1 v2 = 4'd3;
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#1 b2 = 4;
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#1 s2 = 5;
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#1 i2 = 6;
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#1 l2 = 7;
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#1 r = 8.0;
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#1 ->e;
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// NOTE: the value change callback on a part select returns the value of the entire variable.
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#1 p4 = 4'd10;
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#1 a4[0] = 4'd11;
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#1 a4[1] = 4'd12;
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#1 a2[0] = 4'd13;
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#1 a2[1] = 4'd14;
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end
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endmodule
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