52 lines
1.4 KiB
VHDL
52 lines
1.4 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- @author Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- 'wait on' & 'wait until' test
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_wait is
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port(a : in std_logic_vector(1 downto 0);
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b : out std_logic_vector(1 downto 0));
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end vhdl_wait;
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architecture test of vhdl_wait is
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begin
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process begin
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report "final wait test";
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wait;
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end process;
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process begin
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wait on a(0);
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report "wait 1 completed";
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-- acknowledge wait 1
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b(0) <= '1';
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end process;
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process begin
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wait until(a(1) = '1' and a(1)'event);
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report "wait 2 completed";
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-- acknowledge wait 2
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b(1) <= '1';
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end process;
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end test;
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