66 lines
2.0 KiB
VHDL
66 lines
2.0 KiB
VHDL
-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Tests initialization of records with aggregate expressions.
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-- (based on the vhdl_struct_array test)
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_record_elab is
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port (
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i_low0: in std_logic_vector (3 downto 0);
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i_high0: in std_logic_vector (3 downto 0);
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i_low1: in std_logic_vector (3 downto 0);
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i_high1: in std_logic_vector (3 downto 0);
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o_low0: out std_logic_vector (3 downto 0);
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o_high0: out std_logic_vector (3 downto 0);
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o_low1: out std_logic_vector (3 downto 0);
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o_high1: out std_logic_vector (3 downto 0)
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);
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end vhdl_record_elab;
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architecture test of vhdl_record_elab is
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type word is record
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high: std_logic_vector (3 downto 0);
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low: std_logic_vector (3 downto 0);
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end record;
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type dword is array (1 downto 0) of word;
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signal my_dword : dword;
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signal dword_a : dword;
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begin
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-- inputs
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my_dword(0) <= (low => i_low0, high => i_high0);
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-- test if you can assign values in any order
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my_dword(1) <= (high => i_high1, low => i_low1);
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dword_a <= (0 => (low => "0110", high => "1001"),
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1 => (high => "1100", low => "0011"));
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-- outputs
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o_low0 <= my_dword(0).low;
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o_high0 <= my_dword(0).high;
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o_low1 <= my_dword(1).low;
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o_high1 <= my_dword(1).high;
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end test;
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