23 lines
336 B
VHDL
23 lines
336 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity not_func is
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port (
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a_i : in std_logic;
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c_o : out std_logic
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);
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end not_func;
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architecture rtl of not_func is
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function invert (
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i : std_logic
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) return std_logic is
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begin
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return not i;
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end function invert;
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begin
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c_o <= invert(a_i);
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end architecture rtl;
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