43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for expression concatenation in VHDL.
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module concat_test;
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concat dut();
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initial begin
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#1; // wait for signal assignments
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if(dut.concat1 !== 2'b10)
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begin
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$display("FAILED: concat1 should be 10 but is %b", dut.concat1);
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$finish();
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end
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if(dut.concat2 !== 5'b11010)
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begin
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$display("FAILED: concat2 should be 11010 but is %b", dut.concat2);
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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