55 lines
1.0 KiB
Verilog
55 lines
1.0 KiB
Verilog
module test;
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// Test that intra-assignment delay values of 'z and 'x get treated as a zero
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// delay. Check this for different types of assignments. The assignment should
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// not be skipped.
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reg failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED(%0d): `%s`, expected %0x, got %0x", `__LINE__, `"expr`", val, expr); \
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failed = 1'b1; \
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end
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integer delay_x = 32'hx;
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wire [31:0] delay_z;
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reg [31:0] x;
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reg [31:0] a[0:1];
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integer i = 0, j = 0;
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`define test(var) \
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// Non-blocking \
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var = 0; \
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var <= #delay_x 1; \
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#1 `check(var, 1) \
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var = 0; \
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var <= #delay_z 1; \
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#1 `check(var, 1) \
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// blocking \
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var = 0; \
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var = #delay_x 1; \
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`check(var, 1) \
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var = 0; \
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var = #delay_z 1; \
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`check(var, 1)
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initial begin
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`test(x)
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`test(x[0])
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`test(x[i])
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`test(a[0])
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`test(a[0][0])
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`test(a[0][j])
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`test(a[i])
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`test(a[i][0])
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`test(a[i][j])
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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