14 lines
350 B
Verilog
14 lines
350 B
Verilog
// NOTE: The expected results for this test will depend on the order in
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// which the compiler elaborates the statements.
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module top;
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uwire [7:0] w;
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assign w[5:2] = 4'd0;
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assign w[1:0] = 2'd1;
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assign w[3:2] = 2'd1;
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assign w[5:4] = 2'd1;
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assign w[7:6] = 2'd1;
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initial $display("Failed: this should be a compile time error!");
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endmodule
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