40 lines
1016 B
Verilog
40 lines
1016 B
Verilog
// Check that when timing checks are disabled (or in the case of Icarus Verilog not supported)
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// that the delayed reference and data signals become copies of the original reference and data signals
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module test;
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wire sig1, sig2, del_sig1, del_sig2, del_sig3, del_sig4, notifier, cond1, cond2;
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assign sig1 = 1'b0;
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assign sig2 = 1'b1;
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specify
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$setuphold(posedge sig1, negedge sig2 , 0:0:0 , 0:0:0 , notifier , cond1 , cond2 , del_sig1 , del_sig2 ) ;
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/*
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Internally the simulator does the following:
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assign del_sig1 = sig1;
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assign del_sig2 = sig2;
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*/
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$recrem(posedge sig1, negedge sig2 , 0:0:0 , 0:0:0 , notifier, cond1 , cond2 , del_sig3 , del_sig4 );
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/*
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Internally the simulator does the following:
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assign del_sig3 = sig1;
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assign del_sig4 = sig2;
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*/
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endspecify
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initial begin
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if (del_sig1 == 1'b0 && del_sig2 == 1'b1 && del_sig3 == 1'b0 && del_sig4 == 1'b1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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