54 lines
1.4 KiB
Verilog
54 lines
1.4 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Check posedge vector - should use bit 0 only. Doesn't work with XL
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module time2 ();
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reg [3:0] clock;
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reg [3:0] b;
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reg [3:0] count;
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initial
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begin
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b = 4'b1111;
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count = 0;
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for (clock = 0; clock<=10; clock = clock + 1)
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begin
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$display("time = %t, clock = %h",$time,clock);
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#10;
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end
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end
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always @(posedge clock & b)
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begin
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count = count+1;
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$display(" edge ! time = %t, count = %h",$time,count);
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end
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initial
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begin
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#1000;
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if(count != 6)
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$display("FAILED - vect[0] clock detect count=%d",count);
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else
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$display("PASSED");
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end
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endmodule
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