51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
module main;
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reg src;
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reg clk;
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wire dst0, dst1;
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test #(.parm(0)) test0 (.dst(dst0), .src(src), .clk(clk));
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test #(.parm(1)) test1 (.dst(dst1), .src(src), .clk(clk));
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//Note: For Modelsim compatibility do instantiation as:
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//test #(.parm(2'b10)) test0 (.dst(dst0), .src(src), .clk(clk));
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//test #(.parm(2'b11)) test1 (.dst(dst1), .src(src), .clk(clk));
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//The reason is that Modelsim handles single-bit std_logic as an
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//enumeration, and enumeration values 2 and 3 correspond to the
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//stdlogic '0' and '1' values. The integer to std_logic values
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//in modelsim are:
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// 0 - 'U'
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// 1 - 'X'
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// 2 - '0'
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// 3 - '1'
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// 4 - 'Z'
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// 5 - 'W'
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// 6 - 'L'
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// 7 - 'H'
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// 8 - '-'
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//Maybe in the future we'll have to do something similar?
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initial begin
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clk = 0;
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src = 0;
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#1 clk = 1;
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#1 if (dst0 !== 1'b0 || dst1 !== 1'b1) begin
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$display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1);
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$finish;
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end
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clk = 0;
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src = 1;
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#1 clk = 1;
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#1 if (dst0 !== 1'b1 || dst1 !== 1'b0) begin
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$display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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