17 lines
323 B
Verilog
17 lines
323 B
Verilog
// Check that declaring an integer typed non-ANSI task port for signal that was
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// previously declared as a variable is an error. Even if the types for both
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// declarations are the same.
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module test;
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task t;
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integer x;
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input integer x;
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$display("FAILED");
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endtask
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integer y;
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initial t(y);
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endmodule
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