18 lines
310 B
Verilog
18 lines
310 B
Verilog
// Check that declaring two non-ANSI task ports with an implicit type and the
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// same name is an error. Even if the signal was previously declared as an
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// variable.
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module test;
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task t;
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integer x;
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input x;
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input x;
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$display("FAILED");
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endtask
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integer y;
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initial t(y, y);
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endmodule
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