34 lines
647 B
Verilog
34 lines
647 B
Verilog
// Check that null-bytes are ignored when assigning to an element of a string
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// type variable.
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module test;
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reg failed = 1'b0;
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`define check(val, exp) \
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if (val != exp) begin \
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$display("FAILED(%0d): Expected '%0s', got '%0s'.", `__LINE__, exp, val); \
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failed = 1'b1; \
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end
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string s;
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byte x;
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initial begin
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s = "Test";
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s[1] = 8'h00; // This should be ignored
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`check(s, "Test");
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s[1] = "\000"; // This should be ignored
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`check(s, "Test");
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x = 8'h00;
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s[1] = x; // This should be ignored
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`check(s, "Test");
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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