44 lines
759 B
Verilog
44 lines
759 B
Verilog
// Check that null-bytes are removed when converting to string type.
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module test;
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reg failed = 1'b0;
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`define check(val, exp) \
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if (val != exp) begin \
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$display("FAILED(%0d): Expected '%0s', got '%0s'.", `__LINE__, exp, val); \
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failed = 1'b1; \
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end
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string s;
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reg [47:0] x;
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initial begin
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s = "\000a\000b\000";
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`check(s, "ab");
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s = string'("\000a\000b\000");
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`check(s, "ab");
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s = string'(48'h0061006200);
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`check(s, "ab");
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x = 48'h0061006200;
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s = string'(x);
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`check(s, "ab");
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s = "cd";
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s = {s, "\000a\000b\000"};
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`check(s, "cdab");
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s = "cd";
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s = {"\000a\000b\000", s};
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`check(s, "abcd");
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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