17 lines
392 B
Verilog
17 lines
392 B
Verilog
// Check that package scoped identifiers lookup does not cross the package
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// boundary.
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package P;
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endpackage
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module test;
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int x;
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initial begin
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int y;
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y = P::test.x; // This should fail. test.x is visible from within the
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// package, but it can not be accessed through a package
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// scoped identifier.
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$display("FAILED");
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end
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endmodule
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