20 lines
351 B
Verilog
20 lines
351 B
Verilog
// Check that the width of a package scoped function is reported correctly.
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package P;
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function bit [22:0] s();
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return 0;
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endfunction
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endpackage
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module test;
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initial begin
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if ($bits(P::s()) == 23) begin
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$display("PASSED");
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end else begin
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$display("FAILED $bits(P::s()) = %0d", $bits(P::s()));
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end
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end
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endmodule
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