30 lines
423 B
Verilog
30 lines
423 B
Verilog
// Check that continuous array assignments from package scoped identifiers are
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// supported.
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package P;
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reg [3:0] y[2];
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task init;
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y[0] = 1;
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y[1] = 2;
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endtask
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endpackage
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module test;
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import P::init;
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wire [3:0] x[2];
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assign x = P::y;
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initial begin
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init();
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if (x[0] === 1 && x[1] === 2) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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