19 lines
371 B
Verilog
19 lines
371 B
Verilog
// Check that binding task arguments by name is supported and that a mix of
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// positional and named arguments is supported.
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module test;
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task t(integer a, integer b, integer c);
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if (a == 1 && b == 2 && c == 3) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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endtask
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initial begin
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t(1, .c(3), .b(2));
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end
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endmodule
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