50 lines
816 B
Verilog
50 lines
816 B
Verilog
// Check that it is possible to declare module ports without specifing the
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// direction.
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bit failed = 1'b0;
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`define check(val, exp) do begin \
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if ((val) !== (exp)) begin \
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$display("FAILED(%0d): Expected `%d`, got `%d`.", `__LINE__, \
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(exp), (val)); \
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failed = 1'b1; \
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end \
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end while (0)
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// All ports should be inout if no direction is specified
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module M (wire [31:0] a, b, c);
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assign c = a ^ b;
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initial begin
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`check($bits(a), 32);
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`check($bits(b), 32);
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`check($bits(c), 32);
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end
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endmodule
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module test;
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wire [31:0] a, b, c;
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M i_m (a, b, c);
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`define A 'h01234567
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`define B 'hfedcba98
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assign a = `A;
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assign b = `B;
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initial begin
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#1
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`check(c, `A ^ `B);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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