35 lines
485 B
Verilog
35 lines
485 B
Verilog
// Check vector part cannot be both procedurally and continuously assigned.
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module test();
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logic [7:0] v;
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assign v[5:2] = 4'd0;
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integer lsb = 0;
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integer msb = 7;
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initial begin
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v[1:0] = 2'd1;
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v[3:2] = 2'd1;
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v[5:4] = 2'd1;
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v[7:6] = 2'd1;
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v[0 +: 2] = 2'd2;
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v[2 +: 2] = 2'd2;
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v[5 -: 2] = 2'd2;
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v[7 -: 2] = 2'd2;
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v[lsb +: 2] = 2'd3;
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v[msb -: 2] = 2'd3;
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v[0] = 1'b1;
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v[2] = 1'b1;
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v[4] = 1'b1;
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v[6] = 1'b1;
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v[lsb] = 1'b1;
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v[msb] = 1'b1;
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end
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endmodule
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