41 lines
1000 B
Verilog
41 lines
1000 B
Verilog
// Check different parts of a variable can be procedurally and continuously assigned.
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module test();
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logic [11:0] v;
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assign v[7:4] = 4'd1;
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reg failed = 0;
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initial begin
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v[11:8] = 4'd2;
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#0 $display("%b", v);
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if (v !== 12'b00100001xxxx) failed = 1;
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/*
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* IEEE 1800-2017 states that "A force or release statement shall not be
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* applied to a variable that is being assigned by a mixture of continuous
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* and procedural assignments.", but some other compilers allow this. It
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* looks to be more work to detect and report it as an error than to allow
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* it.
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*/
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force v[7:4] = 8'd3;
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#0 $display("%b", v);
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if (v !== 12'b00100011xxxx) failed = 1;
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force v[11:8] = 8'd4;
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#0 $display("%b", v);
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if (v !== 12'b01000011xxxx) failed = 1;
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release v[7:4];
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#0 $display("%b", v);
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if (v !== 12'b01000001xxxx) failed = 1;
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release v[11:8];
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#0 $display("%b", v);
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if (v !== 12'b01000001xxxx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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