27 lines
415 B
Verilog
27 lines
415 B
Verilog
// Check that implicitly imported identifiers can be exported through a package
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// wildcard export.
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package P1;
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integer x = 123;
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endpackage
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package P2;
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import P1::*;
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export P1::*;
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integer y = x; // Creates an import for P1::x
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endpackage
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module test;
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import P2::x;
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initial begin
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if (x == 123) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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