29 lines
589 B
Verilog
29 lines
589 B
Verilog
// Check that dynamic arrays with compatible packed base types can be assigned
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// to each other. Even if the element types are not identical.
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module test;
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typedef bit [31:0] T1;
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typedef bit [31:0] T2[];
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// For two packed types to be compatible they need to have the same packed
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// width, both be 2-state or 4-state and both be either signed or unsigned.
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bit [32:1] d1[];
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bit [7:0][3:0] d2[];
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int unsigned d3[];
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T1 d4[];
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T2 d5;
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initial begin
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d1 = new[1];
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d2 = d1;
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d3 = d2;
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d4 = d3;
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d5 = d4;
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d1 = d5;
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$display("PASSED");
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end
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endmodule
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