46 lines
739 B
Verilog
46 lines
739 B
Verilog
// Check that it is possible to access static properties of a base class
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class B;
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static int x = 0;
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static int y = 0;
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endclass
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class C extends B;
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task t(int a, int b);
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x = a;
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this.y = b;
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endtask
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function int f;
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return x + this.y;
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endfunction
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endclass
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module test;
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bit failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED: `%s`, expected %b, got %b", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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C c = new;
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initial begin
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// Check access inside the class
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c.t(10, 20);
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`check(c.f(), 30)
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// Check access outside of the class
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c.x = 40;
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`check(c.x, 40)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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