36 lines
491 B
Verilog
36 lines
491 B
Verilog
// Check that automatic 2-state variables are initialized to 0.
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module test;
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bit failed = 1'b0;
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function automatic int f(int x);
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int a;
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if (a !== 0) begin
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failed = 1'b1;
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end
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return x;
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endfunction
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task automatic t;
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int a;
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if (a !== 0) begin
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failed = 1'b1;
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end
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endtask
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initial begin
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int x;
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t;
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x = f(10);
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if (failed) begin
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$display("FAILED");
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end else begin
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$display("PASSED");
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end
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end
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endmodule
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