17 lines
337 B
Verilog
17 lines
337 B
Verilog
// Check that continuous assignment of two compatible arrays is supported, even
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// if the element types are not identical and one is a built-in integer and the
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// other a equivalent packed type.
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module test;
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wire signed [31:0] x[1:0];
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wire integer y[1:0];
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assign x = y;
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initial begin
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$display("PASSED");
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end
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endmodule
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