45 lines
901 B
Verilog
45 lines
901 B
Verilog
// Check that continuous assignment of unpacked array assignment patterns is
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// supported and entries are assigned in the right order.
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module test;
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bit failed;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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int x[3:0];
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int y[0:3];
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int z[4];
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assign x = '{1'b1, 1 + 1, 3.3, "TEST"};
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assign y = '{1'b1, 1 + 1, 3.3, "TEST"};
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assign z = '{1'b1, 1 + 1, 3.3, "TEST"};
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initial begin
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`check(x[0], 1413829460);
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`check(x[1], 3);
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`check(x[2], 2);
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`check(x[3], 1);
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`check(y[0], 1);
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`check(y[1], 2);
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`check(y[2], 3);
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`check(y[3], 1413829460);
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`check(z[0], 1);
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`check(z[1], 2);
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`check(z[2], 3);
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`check(z[3], 1413829460);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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