35 lines
692 B
Verilog
35 lines
692 B
Verilog
// Check that positional assigment patterns are supported for structs when using
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// continuous assignments.
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module test;
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typedef struct packed {
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logic [31:0] x;
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logic [15:0] y;
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logic [7:0] z;
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} T;
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T x;
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// Check nested assignment patterns
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struct packed {
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T x;
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logic [2:0][3:0] y;
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} y;
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assign x = '{1'b1, 2.0, 2 + 1};
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assign y = '{'{1'b1, 2.0, 2 + 1}, '{4, 5, 6}};
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// Use an inital block with a delay since a final block cannot be converted to vlog95
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initial begin
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#1;
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if (x === 56'h00000001000203 &&
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y === 68'h00000001000203456) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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