22 lines
517 B
Verilog
22 lines
517 B
Verilog
// Check that positional assignment patterns are supported for packed arrays
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// when doing continuous assignments to array elements.
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module test;
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wire [3:0][3:0] x[2];
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wire [1:0][3:0][3:0] y[2];
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assign x[0] = '{1'b1, 32'h2, 3.0, "TEST"};
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assign y[1] = '{'{1'b1, 1 + 1, 3.0, "TEST"},
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'{5, 6, '{1'b0, 1 * 1, 3, 1.0}, 8}};
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final begin
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if (x[0] === 16'h1234 && y[1] == 32'h12345678) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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