35 lines
643 B
Verilog
35 lines
643 B
Verilog
// Check that the initial value of a 2-state array is properly propagated
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module test;
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bit failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED(%0d): `%s`, expected %0d, got %0d", `__LINE__, `"expr`", val, expr); \
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failed = 1'b1; \
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end
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bit [1:0] a[2];
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integer i = 0;
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wire [1:0] x = a[0];
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wire [1:0] y = a[i];
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wire [2:0] z = {1'b1, a[0]};
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wire w = a[0][0];
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initial begin
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#1;
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`check(a[0], 2'b00);
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`check(x, 2'b00);
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`check(y, 2'b00);
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`check(z, 3'b100);
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`check(w, 1'b0);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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