70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
// Check that the width on a nested struct member is calculated correctly
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module test;
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bit failed = 1'b0;
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`define check(expr, val) do \
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if (expr !== val) begin \
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$display("FAILED(%0d): `%s`, expected %0d, got %0d", `__LINE__, `"expr`", val, expr); \
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failed = 1'b1; \
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end \
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while (0)
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typedef enum bit [15:0] {
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A, B
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} E;
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struct packed {
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struct packed {
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struct packed {
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reg [7:0][3:0] x;
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E e;
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} s2;
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int z;
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} s1;
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int y;
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} s0;
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initial begin
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`check($bits(s0), 112);
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`check($bits(s0.s1), 80);
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`check($bits(s0.s1.s2), 48);
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`check($bits(s0.s1.s2.x), 32);
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`check($bits(s0.s1.s2.e), 16);
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`check($bits(s0.s1.s2.e.next), 16);
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`check($bits(s0.s1.s2.e.prev), 16);
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`check($bits(s0.s1.s2.e.first), 16);
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`check($bits(s0.s1.s2.e.last), 16);
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`check($bits(s0.s1.s2.e.num), 32);
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`check($bits(s0[0]), 1);
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`check($bits(s0.s1[0]), 1);
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`check($bits(s0.s1.s2[0]), 1);
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`check($bits(s0.s1.s2.x[0]), 4);
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`check($bits(s0.s1.s2.x[0][0]), 1);
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`check($bits(s0.s1.s2.e[0]), 1);
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`check($bits(s0[1:0]), 2);
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`check($bits(s0.s1[1:0]), 2);
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`check($bits(s0.s1.s2[1:0]), 2);
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`check($bits(s0.s1.s2.x[1:0]), 8);
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`check($bits(s0.s1.s2.x[0][1:0]), 2);
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`check($bits(s0.s1.s2.e[1:0]), 2);
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`check($bits(s0[0+:2]), 2);
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`check($bits(s0.s1[0+:2]), 2);
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`check($bits(s0.s1.s2[0+:2]), 2);
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`check($bits(s0.s1.s2.x[0+:2]), 8);
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`check($bits(s0.s1.s2.x[0][0+:2]), 2);
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`check($bits(s0.s1.s2.e[0+:2]), 2);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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