24 lines
493 B
Verilog
24 lines
493 B
Verilog
module main;
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typedef struct packed {
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logic [15:8] f;
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} structtype;
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structtype s;
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initial
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begin
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$display("$left(s.f) = %2d, $right(s.f) = %2d", $left(s.f), $right(s.f));
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if ($left(s.f) !== 15) begin
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$display("FAILED -- $left(s.f) = %2d", $left(s.f));
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$finish;
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end
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if ($right(s.f) !== 8) begin
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$display("FAILED -- $right(s.f) = %2d", $right(s.f));
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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