25 lines
463 B
Verilog
25 lines
463 B
Verilog
module main;
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typedef enum logic [2:0] {
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ENUM_VAL = 3'b110
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} enumtype;
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typedef struct packed {
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enumtype e;
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} structtype;
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structtype s;
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initial
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begin
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s.e = ENUM_VAL;
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$display("s.e[2] = %d, s.e[1] = %d, s.e[0] = %d", s.e[2], s.e[1], s.e[0]);
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if ((s.e[2] != 1'b1) || (s.e[1] != 1'b1) || (s.e[0] != 1'b0)) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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