39 lines
664 B
Verilog
39 lines
664 B
Verilog
// Check that the empty string "" is equivalent to 8'h00
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module test;
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reg failed = 1'b0;
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`define check(val, exp) \
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if (val != exp) begin \
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$display("FAILED(%0d): Expected '%0s', got '%0s'.", `__LINE__, exp, val); \
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failed = 1'b1; \
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end
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reg [47:0] s;
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reg [7:0] x;
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wire [7:0] y;
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assign y = "";
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initial begin
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`check("", 8'h00);
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`check($bits(""), 8);
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$sformat(s, ":%s:%0s:", "", "");
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`check(s, ": ::");
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x = 8'h00;
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$sformat(s, ":%s:%0s:", x, x);
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`check(s, ": ::");
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$sformat(s, ":%s:%0s:", y, y);
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`check(s, ": ::");
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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