32 lines
569 B
Verilog
32 lines
569 B
Verilog
module SingleElementArray(
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input wire [48:0] x1,
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output wire [48:0] out
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);
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wire [48:0] x17[0:0];
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assign x17[0] = x1;
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assign out = {x17[0]};
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endmodule
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module testbench;
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reg [48:0] in;
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wire [48:0] out;
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SingleElementArray dut(.x1(in), .out(out));
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initial begin
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in = 49'h0000000000000;
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#1;
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if (out != 49'h0000000000000) begin
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$display("FAILED");
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$finish;
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end
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in = 49'h1555555555555;
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#1;
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if (out != 49'h1555555555555) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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