26 lines
376 B
Verilog
26 lines
376 B
Verilog
/* Based on PR#848 */
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module err ();
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reg clk;
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initial begin
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clk = 1'b1;
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#3 forever #10 clk=~clk;
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end
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reg [31:0] mem [10:0];
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wire [32:0] kuku = {1'b0,mem[3]};
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always @(posedge clk) begin
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if (kuku !== 33'h0_xx_xx_xx_xx) begin
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$display("FAILED -- kuku has wrong value %h", kuku);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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