35 lines
796 B
Verilog
35 lines
796 B
Verilog
module test();
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parameter N_CH = 1;
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reg pass = 1'b1;
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reg clk;
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reg [31:0] data[0: N_CH-1];
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generate
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genvar i;
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for (i=0; i<N_CH; i = i + 1)
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begin: sdac
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always @ (posedge clk)
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data[i] <= 32'h0;
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end
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endgenerate
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initial
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begin
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clk = 0;
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if (data[0] != 32'bx) begin
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$display("FAILED: initial value, expected 32'bx, got %b", data[0]);
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pass = 1'b0;
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end
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#26 // Check after the first clock edge.
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if (data[0] != 32'b0) begin
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$display("FAILED: final value, expected 32'b0, got %b", data[0]);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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always #25 clk = ~clk;
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endmodule // test
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