25 lines
622 B
Verilog
25 lines
622 B
Verilog
/*
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* partsel_outside_const
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* Check that base_const ± bit_number in a part-select does not wrap around
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* within the internal 32 bit (signed) vector address space.
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* This could incorrectly select bits from a vector when unsized literal
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* constant numbers are used in the part-select index expression.
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*/
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module main;
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reg [1:0] arr = 1;
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wire [1:0] outside_const = arr[-'d1 +: 2];
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initial begin
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if (outside_const !== 'x) begin
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$display("FAILED -- const base_expr out of bounds value %b != xx", outside_const);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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