24 lines
382 B
Verilog
24 lines
382 B
Verilog
// Check that initializers values are supported for module array ports
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module M (
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input [31:0] x[0:1] = '{1, 2},
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output reg [31:0] y[0:1] = '{3, 4}
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);
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initial begin
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#1
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if (x[0] === 1 && x[1] === 2 && y[0] === 3 && y[1] === 4) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module test;
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M i_m ();
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endmodule
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