17 lines
329 B
Verilog
17 lines
329 B
Verilog
// Check that a '*' or '/' following a C-style comment is supported in a macro
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`define x(a, b) a /* comment */ * b
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`define y(a, b) a /* comment */ / b
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module test;
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initial begin
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if (`x(2, 3) === 6 && `y(8, 2) === 4) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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