18 lines
412 B
Verilog
18 lines
412 B
Verilog
module test();
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`define MACRO \
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$display("file %s line %0d", \
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`__FILE__, `__LINE__);
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initial begin
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$display("file %s line %0d", `__FILE__, `__LINE__);
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`line 1 "real_source.v" 0
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$display("file %s line %0d", `__FILE__, `__LINE__);
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`include "line_directive_inc.v"
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$display("file %s line %0d", `__FILE__, `__LINE__);
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`MACRO
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$display("file %s line %0d", `__FILE__, `__LINE__);
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end
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endmodule
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