48 lines
1.1 KiB
Verilog
48 lines
1.1 KiB
Verilog
module top;
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parameter pval = 7;
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string sval, strvb, strcb, strvw, strcw;
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real ridx;
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integer in;
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reg cavb, cacb, cavw, cacw;
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reg vvb, vcb, vvw, vcw;
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reg pvb, pcb, pvw, pcw;
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reg svb, scb, svw, scw;
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integer calvb, calcb, calvw, calcw;
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integer vlvb, vlcb, vlvw, vlcw;
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assign cavb = in[ridx-:1];
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assign cacb = in[0.5-:1];
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assign cavw = in[1-:ridx];
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assign cacw = in[1-:0.5];
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assign calvb[ridx-:1] = 1'b1;
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assign calcb[0.5-:1] = 1'b1;
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assign calvw[1-:ridx] = 1'b1;
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assign calcw[1-:0.5] = 1'b1;
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initial begin
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in = 7;
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ridx = 0.5;
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sval = "ABC";
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vvb = in[ridx-:1];
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vcb = in[0.5-:1];
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vvw = in[1-:ridx];
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vcw = in[1-:0.5];
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vlvb[ridx-:1] = 1'b1;
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vlcb[0.5-:1] = 1'b1;
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vlvw[1-:ridx] = 1'b1;
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vlcw[1-:0.5] = 1'b1;
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pvb = pval[ridx-:1];
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pcb = pval[0.5-:1];
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pvw = pval[1-:ridx];
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pcw = pval[1-:0.5];
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svb = sval[ridx-:1];
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scb = sval[0.5-:1];
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svw = sval[1-:ridx];
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scw = sval[1-:0.5];
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strvb[ridx-:1] = "a";
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strcb[0.5-:1] = "a";
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strvw[1-:ridx] = "a";
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strcw[1-:0.5] = "a";
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end
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endmodule
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