42 lines
863 B
Verilog
42 lines
863 B
Verilog
// Check that it is possible to call functins with empty arguments if they have
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// default values. Check that this works if the function call is part of a force
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// statement in an automatic context.
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module test;
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bit failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED. %s, expected %d, got %d", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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integer x, y, z, w;
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function automatic integer f(integer a = 1, integer b = 2, integer c = 3);
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return a * 100 + b * 10 + c;
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endfunction
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task automatic t;
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force x = f(4, , 6);
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force y = f(4, 5, );
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force z = f(4, , );
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force w = f( , , 6);
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endtask
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initial begin
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t;
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`check(x, 426);
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`check(y, 453);
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`check(z, 423);
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`check(w, 126);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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