16 lines
433 B
Verilog
16 lines
433 B
Verilog
module top;
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real rval;
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integer res;
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reg [7:0] rg;
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reg [7:0] mem [3:0];
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initial begin
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res = $fread(rval, 1); // 1st arg. must be a reg. or memory.
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res = $fread(rg); // Too few argument.
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res = $fread(mem, "a"); // Not a valid fd.
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res = $fread(mem, 1, "a"); // Not a valid start.
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res = $fread(mem, 1, 0, "a"); // Not a valid count.
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res = $fread(mem, 1, 0, 2, 3); // Too many argument.
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end
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endmodule
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