20 lines
329 B
Verilog
20 lines
329 B
Verilog
// Check that an error is reported for implicit cast to enum when assigning
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// from an array element.
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module test;
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typedef enum reg [31:0] {
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A, B
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} E;
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E e;
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int ea[2];
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initial begin
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ea[0] = B; // This is OK.
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e = ea[0]; // This should fail. Implicit cast to enum.
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$display("FAILED");
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end
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endmodule
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