24 lines
342 B
Verilog
24 lines
342 B
Verilog
// Check that assigning to a enum types variable from an enum typed class
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// array element works.
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module test;
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typedef enum reg [31:0] {
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A, B
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} E;
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E e;
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E ea[2];
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initial begin
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ea[0] = B;
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e = ea[0];
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if (e === B) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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