17 lines
321 B
Verilog
17 lines
321 B
Verilog
// Test we detect and report circular dependencies.
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// Strictly speaking this is not legal as it uses a hierarchical name in a
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// constant expression,
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module test;
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reg [$bits(test.b):1] a;
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reg [$bits(test.a):1] b;
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initial begin
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// This test is expected to fail at compile time.
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$display("FAILED");
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end
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endmodule
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