28 lines
371 B
Verilog
28 lines
371 B
Verilog
// Strictly speaking this is not legal as it uses a hierarchical name in a
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// constant expression,
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module test1;
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reg [$bits(test2.v):1] v;
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endmodule
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module test2;
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reg [7:0] v;
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initial begin
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if ($bits(test1.v) === 8 && $bits(test3.v) === 8)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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module test3;
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reg [$bits(test2.v):1] v;
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endmodule
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