26 lines
407 B
Verilog
26 lines
407 B
Verilog
// Icarus elaborates signals in alphabetical order, so force early
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// elaboration that way.
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module test;
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localparam LSB = 0;
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localparam MSB = 7;
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reg [MSB:LSB] c;
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reg [$bits(c):1] a;
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localparam WIDTH = $bits(c);
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reg [WIDTH:1] b;
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initial begin
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$display("a = %b", a);
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$display("b = %b", b);
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if ($bits(a) === 8 && $bits(b) == 8)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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